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k4s56323lf - f(h)e/n/s/c/l/r may 2004 1 mobile-sdram ? vdd/vddq = 2.5v/2.5v ? lvcmos compatible with multiplexed address. ? four banks operation. ? mrs cycle with address key programs. -. cas latency (1, 2 & 3). -. burst length (1, 2, 4, 8 & full page). -. burst type (sequential & interleave). ? emrs cycle with address key programs. ? all inputs are sampled at the positive going edge of the system clock. ? burst read single-bit write operation. ? special function support. -. pasr (partial array self refresh). -. internal tcsr (temperature compensated self refresh) ? dqm for masking. ? auto refresh. ? 64ms refresh period (4k cycle). ? commercial temperature operation (-25 c ~ 70 c). ? extended temperature operation (-25 c ~ 85 c). ? 90balls fbga ( -fxxx -pb, -hxxx -pb free). features the k4s56323lf is 268,435,456 bits synchronous high data rate dynamic ram organized as 4 x 2,097,152 words by 32 bits, fabricated with samsung?s high performance cmos technol- ogy. synchronous design allows pr ecise cycle control with the use of system clock and i/o tr ansactions are pos sible on every clock cycle. range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high per- formance memory sy stem applications. general description ordering information - f(h)e/n/s : normal/low/super low power, extended temperature(-25 c ~ 85 c) - f(h)c/l/r : normal/low/super low power, commercial temperature(-25 c ~ 70 c) notes : 1. in case of 40mhz frequency, cl1 can be supported. 2. samsung are not designed or manufactured fo r use in a device or system that is us ed under circumstance in which human life i s potentially at stake. please contact to the memory marketing team in samsung el ectronics when considering the use of a product contained herein for any specific pur pose, such as medical, aerospace, nucle ar, military, vehicular or undersea repeater use. part no. max freq. interface package k4s56323lf-f(h)e/n/s/c/l/r60 166mhz(cl=3) lvcmos 90 fbga pb (pb free) k4s56323lf-f(h)e/n/s/c/l/r75 133mhz(cl=3),111mhz(cl=2) k4s56323lf-f(h)e/n/s/c/l/r1h 111mhz(cl=2) k4s56323lf-f(h)e/n/s/c/l/r1l 111mhz(cl=3)*1 2m x 32bit x 4 banks mobile sdram in 90fbga
k4s56323lf - f(h)e/n/s/c/l/r may 2004 2 mobile-sdram bank select data input register 2m x 32 2m x 32 sense amp output buffer i/o control column decoder latency & burst length programming register address register row buffer refresh counter row decoder col. buffer lras lcbr lcke lras lcbr lwe ldqm clk cke cs ras cas we dqm lwe ldqm dqi clk add lcas lwcbr 2m x 32 2m x 32 timing register functional block diagram
k4s56323lf - f(h)e/n/s/c/l/r may 2004 3 mobile-sdram 90ball(6x15) fbga 123789 a dq26 dq24 v ss v dd dq23 dq21 bdq28v ddq v ssq v ddq v ssq dq19 cv ssq dq27 dq25 dq22 dq20 v ddq dv ssq dq29 dq30 dq17 dq18 v ddq ev ddq dq31 nc nc dq16 v ssq fv ss dqm3 a3 a2 dqm2 v dd ga4a5a6a10a0a1 h a7 a8 nc nc ba1 a11 j clk cke a9 ba0 cs ras kdqm1 nc nc cas we dqm0 lv ddq dq8 v ss v dd dq7 v ssq mv ssq dq10 dq9 dq6 dq5 v ddq nv ssq dq12 dq14 dq1 dq3 v ddq pdq11v ddq v ssq v ddq v ssq dq4 r dq13 dq15 v ss v dd dq0 dq2 pin name pin function clk system clock cs chip select cke clock enable a 0 ~ a 11 address ba 0 ~ ba 1 bank select address ras row address strobe cas column address strobe we write enable dqm 0 ~ dqm 3 data input/output mask dq 0 ~ 31 data input/output v dd /v ss power supply/ground v ddq /v ssq data output power/ground package dimension and pin configuration < bottom view *1 > < top view *2 > < top view *2 > symbol min typ max a - 1.10 1.20 a 1 0.27 0.32 0.37 e-8.00- e 1 -6.40- d - 13.00 - d 1 -11.20- e-0.80- b 0.45 0.50 0.55 z--0.10 [unit:mm] 521 63 4 8 97 f e d c b j h g a e d d/2 d 1 e 1 e e/2 z b substrate(2layer) #a1 ball origin indicator m l k r p n k4s56323lf-xxxx samsung week a a1
k4s56323lf - f(h)e/n/s/c/l/r may 2004 4 mobile-sdram dc operating conditions recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 to 85 c for extended, -25 to 70 c for commercial) notes : 1. vih (max) = 3.0v ac.the overshoot voltage duration is 3ns. 2. vil (min) = -1.0v ac. the undershoot voltage duration is 3ns. 3. any input 0v vin vddq. input leakage currents include hi-z output leakage for all bi-directional buffers with tri-state outputs. 4. dout is disabled, 0v vout vddq. parameter symbol min typ max unit note supply voltage v dd 2.3 2.5 2.7 v v ddq 2.3 2.5 2.7 v input logic high voltage v ih 0.8 x v ddq - v ddq + 0.3 v 1 input logic low voltage v il -0.3 0 0.3 v 2 output logic high voltage v oh v ddq -0.2 - - v i oh = -0.1ma output logic low voltage v ol - - 0.2 v i ol = 0.1ma input leakage current i li -10 - 10 ua 3 capacitance (v dd = 2.5v, t a = 23 c, f = 1mhz, v ref =0.9v 50 mv) pin symbol min max unit note clock c clk - 4.0 pf ras , cas , we , cs , cke c in - 4.0 pf dqm c in - 4.0 pf address c add - 4.0 pf dq 0 ~ dq 31 c out - 6.0 pf absolute maximum ratings notes: permanent device damage may occur if absolute maximum ratings are exceeded. functional operation should be restricted to recommended operating condition. exposure to higher than recommended voltage for extended periods of time could affect device reliability. parameter symbol value unit voltage on any pin relative to v ss v in , v out -1.0 ~ 3.6 v voltage on v dd supply relative to v ss v dd , v ddq -1.0 ~ 3.6 v storage temperature t stg -55 ~ +150 c power dissipation p d 1.0 w short circuit current i os 50 ma
k4s56323lf - f(h)e/n/s/c/l/r may 2004 5 mobile-sdram dc characteristics recommended operating conditions (voltage referenced to v ss = 0v, t a = -25 to 85 c for extended, -25 to 70 c for commercial) notes: 1. measured with outputs open. 2. refresh period is 64ms. 3. internal tcsr can be supported. in commercial temp : max 40 c/max 70 c, in extended temp : max 40 c/max 85 c 4. k4s56323lf-f(h)e/c** 5. k4s56323lf-f(h)n/l** 6. k4s56323lf-f(h)s/r** 7. unless otherwise noted, input swing ievei is cmos(vih /vil=vddq/vssq). parameter symbol test condition version unit note -60 -75 -1h -1l operating current (one bank active) i cc1 burst length = 1 t rc t rc (min) i o = 0 ma 110 100 100 90 ma 1 precharge standby current in power-down mode i cc 2p cke v il (max), t cc = 10ns 0.5 ma i cc 2ps cke & clk v il (max), t cc = 0.5 precharge standby current in non power-down mode i cc 2n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 20 ma i cc 2ns cke v ih (min), clk v il (max), t cc = input signals are stable 8 active standby current in power-down mode i cc 3p cke v il (max), t cc = 10ns 4 ma i cc 3ps cke & clk v il (max), t cc = 2 active standby current in non power-down mode (one bank active) i cc 3n cke v ih (min), cs v ih (min), t cc = 10ns input signals are changed one time during 20ns 30 ma i cc 3ns cke v ih (min), clk v il (max), t cc = input signals are stable 20 ma operating current (burst mode) i cc 4 i o = 0 ma page burst 4banks activated t ccd = 2clks 120 100 90 90 ma 1 refresh current i cc 5 t rc t rc (min) 200 180 170 150 ma 2 self refresh current i cc 6 cke 0.2v -e/c 1500 ua 4 -n/l 600 5 -s/r internal tcsr max 40 max 85/70 c 3 full array 450 600 ua 6 1/2 of full array 400 450 1/4 of full array 350 400
k4s56323lf - f(h)e/n/s/c/l/r may 2004 6 mobile-sdram vddq 500 ? 500 ? output 30pf voh (dc) = vddq - 0.2v, ioh = -0.1ma vol (dc) = 0.2v, iol = 0.1ma vtt=0.5 x vddq 50 ? output 30pf z0=50 ? figure 2. ac output load circuit figure 1. dc output load circuit ac operating test conditions (v dd = 2.5v 0.2v, t a = -25 to 85 c for extended, -25 to 70 c for commercial) parameter value unit ac input levels (vih/vil) 0.9 x v ddq / 0.2 v input timing measurement reference level 0.5 x v ddq v input rise and fall time tr/tf = 1/1 ns output timing measurement reference level 0.5 x v ddq v output load condition see figure 2
k4s56323lf - f(h)e/n/s/c/l/r may 2004 7 mobile-sdram operating ac parameter (ac operating conditions unless otherwise noted) notes: 1. the minimum number of clock cycles is determined by dividing the mini mum time required with clock cycle time and then rounding off to the next higher integer. 2. minimum delay is required to complete write. 3. minimum trdl=2clk and tdal(= trdl + trp) is required to complete both of last data write command(trdl) and precharge command (trp). 4. all parts allow every cycle column address change. 5. in case of row precharge interrupt, auto precharge and read burst stop. parameter symbol version unit note -60 -75 -1h -1l row active to row active delay t rrd (min) 12 15 18 18 ns 1 ras to cas delay t rcd (min) 18 18 18 24 ns 1 row precharge time t rp (min) 18 18 18 24 ns 1 row active time t ras (min) 42 45 50 60 ns 1 t ras (max) 100 us row cycle time t rc (min) 60 63 68 84 ns 1 last data in to row precharge t rdl (min) 2 clk 2 last data in to active delay t dal (min) trdl + trp - 3 last data in to new col. address delay t cdl (min) 1 clk 2 last data in to burst stop t bdl (min) 1 clk 2 col. address to col. address delay t ccd (min) 1 clk 4 number of valid output data cas latency=3 2 ea 5 number of valid output data cas latency=2 - 1 number of valid output data cas latency=1 - 0
k4s56323lf - f(h)e/n/s/c/l/r may 2004 8 mobile-sdram ac characteristics (ac operating conditions unless otherwise noted) notes : 1. parameters depend on programmed cas latency. 2. if clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. assumed input rise and fall time (tr & tf) = 1ns. if tr & tf is longer than 1ns, trans ient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter. parameter symbol - 60 - 75 -1h -1l unit note min max min max min max min max clk cycle time cas latency=3 t cc 6.0 1000 7.5 1000 9.0 1000 9.0 1000 ns 1 cas latency=2 t cc - 9.0 9.0 12 cas latency=1 t cc - - - 25 clk to valid output delay cas latency=3 t sac 5.4 6 7 7 ns 1,2 cas latency=2 t sac - 7 7 8 cas latency=1 t sac - - - 20 output data hold time cas latency=3 t oh 2.5 2.5 2.5 2.5 ns 2 cas latency=2 t oh - 2.5 2.5 2.5 cas latency=1 t oh - - - 2.5 clk high pulse width t ch 2.5 2.5 3 3 ns 3 clk low pulse width t cl 2.5 2.5 3 3 ns 3 input setup time t ss 2.0 2.0 2.5 2.5 ns 3 input hold time t sh 1.0 1.0 1.5 1.5 ns 3 clk to output in low-z t slz 1 1 1 1 ns 2 clk to output in hi-z cas latency=3 t shz 5.4 6 7 7 ns cas latency=2 - 7 7 8 cas latency=1 - - - 20
k4s56323lf - f(h)e/n/s/c/l/r may 2004 9 mobile-sdram simplified truth table (v=valid, x=don t care, h=logic high, l=logic low) notes : 1. op code : operand code a0 ~ a11 & ba0 ~ ba1 : program keys. (@mrs) 2. mrs can be issued only at all banks precharge state. a new command can be issued after 2 clk cycles of mrs. 3. auto refresh functions are the same as cbr refresh of dram. the automatical precharge without ro w precharge command is meant by "auto". auto/self refresh can be issued only at all banks precharge state. partial self refresh can be issued only after setting partial self refresh mode of emrs. 4. ba0 ~ ba1 : bank select addresses. 5. during burst read or write with auto precharge, new read/write command can not be issued. another bank read/write command can be issued after the end of burst. new row active of the associated bank can be issued at trp after the end of burst. 6. burst stop command is valid at every burst length. 7. dqm sampled at the positive going edge of clk masks the data- in at that same clk in writ e operation (write dqm latency is 0), but in read operation, it makes the data-out hi-z state after 2 clk cycles. (read dqm latency is 2). command cken-1 cken cs ras cas we dqm ba 0,1 a10/ap a11, a9 ~ a0 note register mode register set h x l l l l x op code 1, 2 refresh auto refresh h h l l l h x x 3 self refresh entry l 3 exit l h l h h h x x 3 h x x x 3 bank active & row addr. h x l l h h x v row address read & column address auto precharge disable h x l h l h x v l column address (a0~a8) 4 auto precharge enable h 4, 5 write & column address auto precharge disable h x l h l l x v l column address (a0~a8) 4 auto precharge enable h 4, 5 burst stop h x l h h l x x 6 precharge bank selection h x l l h l x v l x all banks x h clock suspend or active power down entry h l h x x x x x l v v v exit l h x x x x x precharge power down mode entry h l h x x x x x l h h h exit l h h x x x x l v v v dqm h x v x 7 no operation command h x h x x x x x l h h h
k4s56323lf - f(h)e/n/s/c/l/r may 2004 10 mobile-sdram normal mrs mode test mode cas latency burst type burst length a8 a7 type a6 a5 a4 latency a3 type a2 a1 a0 bt=0 bt=1 0 0 mode register set 0 0 0 reserved 0 sequential 0 0 0 1 1 0 1 reserved 0 0 1 1 1 interleave 0 0 1 2 2 1 0 reserved 0 1 0 2 mode select 0 1 0 4 4 1 1 reserved 0 1 1 3 ba1 ba0 mode 0 1 1 8 8 write burst length 1 0 0 reserved 0 0 setting for nor- mal mrs 1 0 0 reserved reserved a9 length 1 0 1 reserved 1 0 1 reserved reserved 0 burst 1 1 0 reserved 1 1 0 reserved reserved 1 single bit 1 1 1 reserved 1 1 1 full page *3 reserved register programmed with normal mrs address ba0 ~ ba1 a11 ~ a10/ap a9 *2 a8 a7 a6 a5 a4 a3 a2 a1 a0 function "0" setting for normal mrs rfu *1 w.b.l test mode cas latency bt burst length a. mode register field table to program modes register programmed with extended mrs address ba1 ba0 a11 ~ a10/ap a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 function mode select rfu *1 rfu *1 pasr notes: 1. rfu(reserved for future use) should stay "0" during mrs cycle. 2. if a9 is high during mrs cycle, "burst read single bit write" function will be enabled. 3. full page length : x32 : 64mb(256) , 128mb (256), 256mb (512), 512mb (512) mode select pasr ba1 ba0 mode a2 a1 a0 size of refreshed array 0 0 normal mrs 0 0 0 full array 0 1 reserved 0 0 1 1/2 of full array 1 0 emrs for mobile sdram 0 1 0 1/4 of full array 1 1 reserved 0 1 1 reserved reserved address 1 0 0 reserved a11~a10/ap a9 a8 a7 a6 a5 a4 a3 1 0 1 reserved 0 0 0 0 0 0 0 0 1 1 0 reserved 1 1 1 reserved emrs for pasr(partial array self ref.)
k4s56323lf - f(h)e/n/s/c/l/r may 2004 11 mobile-sdram 1. in order to save power consumption, mobile sdram has pasr option. 2. mobile sdram supports 3 kinds of pasr in self refresh mo de : full array, 1/2 of full array and 1/4 of full array. ba1=0 partial self refresh area 1. in order to save power consumption, mobile-dram includes the internal temperature sonsor and control units to control the se lf refresh cycle automatically according to the two temperature range : max 40 c and max 85 c(for extended), max 70 c(for commercial). 2. if the emrs for external tcsr is issued by t he controller, this emrs code for tcsr is ginored. temperature range self refresh current (icc6) unit - e/c - n/l - s/r full array 1/2 of full array 1/4 of full array max 85/70 c 1500 600 600 450 400 ua max 40 c 450 400 350 ba0=0 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 ba1=1 ba0=1 ba1=1 ba0=0 ba1=0 ba0=1 ba1=0 ba0=0 ba1=0 ba0=1 ba1=1 ba0=1 ba1=1 ba0=0 partial array self refresh temperature compensated self refresh b. power up sequence 1. apply power and attempt to maintain cke at a high state and all other inputs may be undefined. - apply vdd before or at the same time as vddq. 2. maintain stable power, stable clock and nop input condition for a minimum of 200us. 3. issue precharge commands for all banks of the devices. 4. issue 2 or more auto-refresh commands. 5. issue a mode register set command to initialize the mode register. 6. issue a extended mode register set command to defi ne pasr operating type of the device after normal mrs. emrs cycle is not mandatory and the emrs comm and needs to be issued only when pasr is used. the default state without emrs command issued is all full array refreshed. the device is now ready for t he operation selected by emrs. for operating with pasr, set pasr mode in emrs setting stage. in order to adjust another mode in the state of pasr mode, addi tional emrs set is required but power up sequence is not needed again at this time. in that case, all banks have to be in idle state prior to adjusting emrs set. - full array - 1/2 array - 1/4 array
k4s56323lf - f(h)e/n/s/c/l/r may 2004 12 mobile-sdram c. burst sequence 1. burst length = 4 initial address sequential interleave a1 a0 0 0 0 1 2 3 0 1 2 3 0 1 1 2 3 0 1 0 3 2 1 0 2 3 0 1 2 3 0 1 1 1 3 0 1 2 3 2 1 0 2. burst length = 8 initial address sequential interleave a2 a1 a0 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0

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